DESIblitz Job: Systems IP – Senior Design Engineer

Systems IP – Senior Design Engineer

Contract,Part Time SHEFFIELD
28/11/2023
  • Applications have closed.

ARM

Working as the System IP team and engaging with the world’s most famous technology companies, we are driving innovation into all areas that compute is possible to help us build better solutions for the billions of people using our technology worldwide!

Role overview:

A Senior Design Engineer will work independently on the development of one or more functional blocks of the IP. They are required to have an understanding across all the elements that enable a products’ successful delivery. This includes low-power design techniques and the awareness of the impact of design decisions on system performance. In addition, they will also have the ability to produce designs that are area efficient, and the verification techniques that are employed to ensure high-quality innovative designs.

Responsibilities:

  • Logic implementation as well as front-end implementation tasks like synthesis, logic equivalence check, and STA
  • The planning, tracking and coordinating of individual tasks to meet high quality goals at the planned time
  • Working closely with the verification team to share the responsibility of delivering high quality hardware designs, including debugging functional or performance issues with the RTL using simulation and debug tools
  • Improving design methodology across the System IP group and wider Arm design community
  • Providing direction and mentoring to other junior members of your team as they learn new things.

Required Skills and Experience:

  • Demonstration of a strong delivery record of high quality, low power, high performance complex micro-architecture and RTL implementations in reasonable timescales.
  • Be able to navigate and make high-level design trade-offs and articulate the rationale for those choices.
  • Knowledgeable on ASIC/FPGA design methodology, IP signoff methods with a deep understanding on timing/area/complexity trade-offs for complex data path designs

'Nice to Have' Skills and Experience:

  • CPU or compute subsystem memory micro-architecture
  • Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI)
  • Experience with any of System Verilog, UVM and formal verification
  • Knowledge of a scripting language such as Perl, Tcl, C shell

In return:

You will get to utilise your engineering skills to build support for the technologies and influence millions of devices for years to come. 

 

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Please Note
At DESIblitz Jobs we strongly believe in helping our candidates find the right job and that everyone should have the same opportunities to find meaningful work. Our ethos is to promote diversity in the workplace. As one of our candidates your background or ethnicity shouldn't have any impact on your ability to apply for this job.

Posted 6 months ago